In a prior art memory architecture, memory cells are arranged in an array or matrix consisting of rows and columns. Each memory cell includes a pass transistor, and read/write word lines are connected to the pass transistors of the memory cells. Read/write bit lines are also connected to the memory cells, and the word lines are used to effectively connect the bit lines to the memory cells. Typically, the word lines are disposed horizontally through the rows of memory cells in the array, and the bit lines are disposed vertically through the columns of memory cells in the array. Each row of memory cells is connected to a single it word line, and each column of memory cells is connected to a single bit line. Therefore, each row of memory cells is associated with a different word line, and each column of memory cells is associated with a different bit line. Sense amplifiers are provided at the bottom of the array, and the bit lines are connected to the sense amplifiers.
This prior art arrangement is illustrated schematically in FIG. 1, wherein the dots 10 in the array represent memory cells, the horizontal lines represent word lines (wherein the array has n word lines), and the vertical lines represent bit lines (wherein the array has m word lines). As shown, each row of memory cells is associated with a different word line, and each column of memory cells is associated with a different bit line. Additionally, sense amplifiers 12 are provided at the bottom of the array, and each bit line is connected to a different sense amplifier. As shown, a decoder 14 is connected to the word lines, and an external device 16 is in communication with the decoder 14. In operation, the external device 16 supplies a memory address to the decoder 14, and the decoder 14 decodes the memory address and turns on a corresponding word line. The word line turns on pass transistors of the memory cells in the respective row of memory cells, and effectively connects the corresponding bit lines to the memory cells in the row.
The access time for a given memory cell is determined, at least in part, by how quickly the bit line which is connected to the memory cell is driven to the correct (i.e. threshold) voltage for the sense amplifier. Typically, the memory cells which are farthest from the sense amplifiers have the slowest access times due to loading on the bit lines.
To reduce access times, a prior art approach provides that a large memory array is effectively divided into a plurality of blocks. Such approach provides that each block has its own set of address decoders, sense amplifiers, column multiplexers (if the memory is implemented using multiple columns) and Input/Output (I/O) drivers, thus increasing the overall size of the memory.